Video Transcoding PCI / PCIe Board Multi-DSP Card for Video Transcoding Applications. Derive the theoretical 16QAM bit error rate with Gray coded constellation mapping in AWGN. Matlab/Octave simulation script also provided. Explore thousands of code examples for MATLAB, Simulink, and other MathWorks products. Bulk ieee projects in vlsi,bulk ieee projects, ieee 2015-16 vlsi projects in chennai, 2015-16 vlsi projects in pondicherry,bulk ieee projects for vlsi,ieee matlab projects in pondicherry,vlsi projects in pondicherry. The bit error rate for binary phase shift keying (BPSK) in AWGN is derived. The simulation scripts in Matlab/Octave also provided. History. Hidden Markov models and the Baum–Welch algorithm were first described in a series of articles by Leonard E. Baum and his peers at the Institute for Defense Analysis in the late 1960s. [1] One of the first major. Mendel HMM Toolbox for Matlab. Written b y Steinar Thorvaldsen, 2004. Last updated: Jan. 2006. Dept. of Mathematics and Statistics. University of Tromsø - Norway. [email protected]. MendelHMM is a Hidden Markov Model (HMM. OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers, while being sent simultaneously. This results in the optimal usage of bandwidth. A set of orthogonal sub-carriers together forms an OFDM. In telecommunication, a convolutional code is a type of error-correcting code that generates parity symbols via the sliding application of a boolean polynomial function to a data stream. The sliding application represents the. VLSI implementation of OFDM modemby Aseem Pandey, Shyam Ratan Agrawalla & Shrikant Manivannanfrom Wipro Technologies. Abstract. OFDM is a multi- carrier system where data bits are encoded to multiple sub- carriers, while being sent simultaneously. This results in the optimal usage of bandwidth. A set of orthogonal sub- carriers together forms an OFDM symbol. To avoid ISI due to multi- path, successive OFDM symbols are separated by guard band. This makes the OFDM system resistant to multi- path effects. Although OFDM in theory has been in existence for a long time, recent developments in DSP and VLSI technologies have made it a feasible option. Many wired and wireless standards like DVBT, DAB, x. DSL and 8. 02. 1. OFDM. This paper first lists various approaches to implement an OFDM system. It then describes the VLSI implementation of OFDM in details. Specifically the 8. OFDM system has been considered in this paper. However, the same considerations would be helpful in implementing any OFDM system in VLSI. Introduction. OFDM is a multi- carrier system where data bits are encoded to multiple sub- carriers. Unlike single carrier systems, all the frequencies are sent simultaneously in time. OFDM offers several advantages over single carrier system like better multi- path effect immunity, simpler channel equalization and relaxed timing acquisition constraints. But it is more susceptible to local frequency offset and radio front- end non- linearities. The frequencies used in OFDM system are orthogonal. Neighboring frequencies with overlapping spectrum can therefore be used. This property is shown in the figure where f. This results inefficient usage of BW. The OFDM is therefore able to provide higher data rate for the same BWOFDM is fast gaining popularity in broadband standards and highspeed wireless LAN. OFDM transceiver. Each sub- carrier in an OFDM system is modulated in amplitude and phase by the data bits. Depending on the kind of modulation technique that is being used, one or more bits are used to modulate each sub- carrier. Modulation techniques typically used are BPSK, QPSK, 1. QAM, 6. 4QAM etc. The process of combining different sub- carriers to form a composite time- domain signal is achieved using Fast Fourier transform. Different coding schemes like block coding, convolutional coding or both are used to achieve better performance in low SNR conditions. Interleaving is done which involves assigning adjacent data bits to non- adjacent bits to avoid burst errors under highly selective fading. Block diagram of an OFDM transceiver is shown below. Figure 1: Block diagram of the 8. OFDM transceiver. Different implementation techniques. Figure 1 shows an OFDM transciever. Following choices are available for imple menting an OFDM system. DSP based implementation DSP based implementation with hardware accelerators VLSI implementation The pros and cons of each approach are explained in the following sections. DSP based implementation. High performance Digital Signal Processors are widely available in the market today. The computer- intensive and time critical functions that were traditionally implemented in hardware are now being implemented in the software running on these processors. Implementing the entire OFDM transceiver in software on DSPs is thus an option to be considered for some applications. It has the following advantages: Reduced development time and quick prototyping. Quick time to market. Flexibility. It can quickly adapt to changing or different standards as it needs only a software change. Ideal for multi- mode Basebands where multiple standards are supported by the same device DSP based implementation has the following disadvantages: Not very optimum in terms of area and power consumption High MIPS requirement. The approximate MIPS requirement for different blocks in OFDM is given below. Module MIPSViterbi decoder 4. FFT 5. 00. NCO 1. Interleaver 1. 50. Channel compensation 1. Scrambler & others 5. The total MIPS requirement is 4. Such high CPU power is not available even with the fastest DSPs in the market today. One way out is parallel processing with multiple DSPs as shown in figure Figure 2: DSP solution. DSP with hardware accelerators. To overcome the MIPS limitation and yet to retain the flexibility of software implementation, some blocks can be implemented in H/W. Figure 3 shows an implementation which can reduce the MIPS requirement by around 4. MIPS. Figure 3: DSP + H/W accelerators. VLSI implementation. Figure 4: VLSI Implementation. In the approach shown in Figure 4 the entire functionality is implemented in hardware. Following are the advantages of this approach: Lower gate count compared to DSP+RAM+ROM, hence lower cost Low power consumption Due to the advantages mentioned above a VLSI based approach was considered for implementation of an 8. Baseband. Following sections describe the VLSI based implementation in details. Design Methodology. The design approach for the OFDM modem is slightly different than a typical ASIC flow. Early in the development cycle, different communication and signal processing algorithms are evaluated for their performance under different conditions like noise, multipath channel and radio non- linearity. Since most of these algorithms are coded in “C” or tools like Matlab, it is important to have a verification mechanism which ensures that the hardware implementation (RTL) is same as the “C” implementation of the algorithm. The flow is shown in the Figure 5. Figure 5: Design flow for Baseband development. Architecture definition. Following points need to be considered in the architecture definition phase. Specifications of the OFDM transceiver Data rates to be supported Range and multipath tolerance Indoor/Outdoor applications Multi- mode: 8. Hiper. LAN/2 Design trade- offs Area – Smaller the die size lesser the chip cost Power – Low power crucial for battery operated mobile devices Ease of implementation – Easy to debug and maintain Customizability – Should be customizable to future standards with variations in OFDM parameters Algorithm survey & simulation. The simulation at algorithmic level is to determine performance of algorithms for various non- linearities and imperfections. The algorithms are tweaked and fine tuned to get the required performance. The following algorithms/parameters are verified. Channel estimation and compensation for different channel models (Rayleigh, Rician, JTC, Two ray) for different delay spreads Correlator performance for different delay spreads and different SNR (AWGN model) Frequency estimation algorithm for different SNR and frequency offsets Compensation for Phase noise and error in Frequency offset estimation System tolerance for I/Q phase and amplitude imbalance FFT simulation to determine the optimum fixed- point widths Wave shaping filter to get the desired spectrum mask Viterbi BER performance for different SNR and traceback length Determine clipping levels for efficient PA use Effect of ADC/DAC width on the EVM and optimum ADC/DAC width Receive AGC Fixed point simulation. One of the decisions needs to be taken early in the design cycle is the format or representation of data. Floating point implementation results in higher hardware costs and additional circuits related with normalizing of numbers. Floating point representa tion is useful when dealing with data of different ranges. However, this is not true as the Baseband circuits have a fair idea of the range of values that they will work on. So a fixed- point representation will be more efficient. Further in fixed point a choice can be made between signed and 2's complement representation. The width of representation need not be constant throughout the Baseband and it depends on the accuracy needed at different points in transmit or receive path. A small change in the number of bits in the representation could result in a significant change in the size of arithmetic circuits especially multipliers. Module Width Gate count. Complex 1. 2 6. KMultiplier 1. KFFT (Radix- 4 with 3 complex multipliers)1. K (excluding RAM)1. K (excluding RAM)Shown below is the loss of SNR due to the decrease in the width of representation. Module Width. SNR d. B (Signal to Quantization noise ratio)ADC8 4. Simulations for different bit- widths tell us which is the optimum bit- width that main tains the required level of accuracy. Significant area and power savings could be made if accurate estimation of fixed- point widths is made. Simulations are performed to determine the required precision. Simulation setup. The algorithms could be simulated in a variety of tools/languages like SPW, MATLAB, “C” or a mix of these. SPW has an exhaustive floating point and fixed- point library. SPW also provides feature to plug- in RTL modules and do a co- simulation of SPW system and Verilog. This helps in verifying the RTL implementation of algorithms against the SPW/C implementation. Hardware design. Interface definition. Baseband interfaces with two external modules: MAC and Radio. Interface to MAC Baseband should support the following for MAC Should support transfer of data at different rates Transmit and receive control RSSI/CCA indication Register programming for power and frequency control Following options are available for MAC interface: Serial data interface – Clock provided along with data. Clock speed changes for different data rates Varying data width, single speed clock – The number of data lines vary accord ing to the data rate. The clock remains same for all rates. Single clock, Parallel data with ready indication – Clock speed and data width is same for all data rates. Ready signal used to indicate valid data Interfaces like SPI/Micro- wire/JTAG could be used for register programming Radio Two kinds of radio interfaces are described below I/Q interface. On the transmit side, the complex Baseband signal is sent to the radio unit that first does a Quadrature modulation followed by up- conversion at 5 GHz.
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